Field of Invention
The present invention relates to a circuit technology, specifically to a digital delay-locked loop and a locking method.
Description of Related Arts
A delay-locked loop (DLL) technology widely used currently is obtained through improvement of a PLL technology, and is widely used in the timing sequence field. It inherits a locked loop technology of a PLL circuit, but removes the oscillator part in the PLL circuit, and instead of this is a delay line with controllable delay amount. The existing general DLL design generally includes a delay line, a state machine and a phase detector, and the state machine adjusts the delay line through output of the phase detector to achieve locking of the output, but faces a harmonic locking problem. In order to solve the harmonic locking problem, the traditional DLL, in design of the delay line, makes the minimum delay time less than one cycle of an input clock signal, and increases a starting circuit to ensure that the DLL is finally locked to one cycle. However, for a high-speed clock signal and a high-resolution digital delay-locked loop, due to its short cycle, more stages of basic delay cells and influences of the circuit parasitic effect, the minimum delay time of the whole delay line usually exceeds one cycle. In this case, the method for the traditional DLL to avoid harmonic periods is no longer applicable.
In view of this, how to design a digital delay-locked loop applicable to that the minimum delay time exceeds one clock cycle becomes a problem to be urgently solved by those skilled in the art.